CS3351 Digital Principles and Computer Organization Previous Year Question Papers - Anna University

UNIT I: COMBINATIONAL LOGIC

Part A (2 Marks)

• What is a Combinational Circuit?
• Define Half Adder and Full Adder.
• What are the limitations of K-map?
• Define Priority Encoder and Multiplexer.
• What is a Decoder?

Part B (13/15 Marks)

• Simplify Boolean expressions using K-map (SOP and POS forms).
• Design a Full Adder using two Half Adders and an OR gate.
• Design a 2-bit or 4-bit Magnitude Comparator.
• Implement Boolean functions using Multiplexer (8x1 MUX).
• Design Encoder and Decoder circuits with logic diagrams.

UNIT II: SYNCHRONOUS SEQUENTIAL LOGIC

Part A (2 Marks)

• Differentiate between Latch and Flip-Flop.
• What is Edge Triggering?
• Compare Moore and Mealy models.
• What are the applications of Shift Registers?
• Define Setup time and Hold time.

Part B (13/15 Marks)

• Explain Master-Slave JK Flip-Flop with diagram.
• Design and analyze Clocked Sequential Circuits.
• Design a Mod-N Synchronous Counter (Mod-5 / Mod-10).
• Explain Shift Registers (SISO, SIPO, PISO, PIPO).
• Design a Binary Counter using Flip-Flops.

UNIT III: COMPUTER FUNDAMENTALS

Part A (2 Marks)

• Define Von Neumann Architecture.
• What is Instruction Set Architecture (ISA)?
• Differentiate Big-Endian and Little-Endian.
• Define Addressing Modes.
• What is Register Transfer Language (RTL)?

Part B (13/15 Marks)

• Explain Functional Units of a Computer with block diagram.
• Discuss various Addressing Modes with examples.
• Explain Instruction Formats (0, 1, 2, 3 address).
• Describe MIPS Architecture and instruction set.
• Explain instruction execution cycle.

UNIT IV: PROCESSOR

Part A (2 Marks)

• Define Pipelining.
• What is Instruction Throughput?
• Define Data Hazard.
• What is Control Hazard?
• List stages of MIPS pipeline.

Part B (13/15 Marks)

• Explain MIPS Datapath with diagram.
• Compare Hardwired vs Microprogrammed Control.
• Explain Pipeline concept and hazards (Data, Control, Structural).
• Discuss techniques to resolve pipeline hazards.
• Explain Branch Prediction techniques.

UNIT V: MEMORY AND I/O SYSTEMS

Part A (2 Marks)

• Define Memory Hierarchy.
• Differentiate SRAM and DRAM.
• What is Cache Memory?
• Define Virtual Memory.
• What is DMA?

Part B (13/15 Marks)

• Explain Cache Mapping Techniques (Direct, Associative, Set-Associative).
• Describe Virtual Memory and address translation.
• Explain DMA Controller with block diagram.
• Discuss Interrupts and Interrupt handling.
• Explain I/O organization and data transfer methods.

Most Repeated / High-Weight Questions

K-map simplification, counter design, addressing modes, pipeline hazards, cache mapping techniques, memory hierarchy, interrupt handling.