EC3552 VLSI and Chip Design Syllabus - Anna University

EC3552 VLSI AND CHIP DESIGN

L T P C

3 0 0 3

COURSE OBJECTIVES:

• To provide fundamental knowledge on MOS devices and its operation
• To provide knowledge on CMOS logic circuits and its design
• To learn the design of basic memories using MOS device
• To understand the design considerations at system and physical level
• To gain knowledge on VLSI design tools and methodologies

UNIT I MOS DEVICES AND CIRCUITS

Basic MOS Technology - nMOS and pMOS Devices, Operation, MOS equations, Device characterization and modeling. Sub-threshold operation and Short channel effects, nMOS and pMOS Inverters - Static and Dynamic characteristics, Inverter Design, noise margins. Pass transistor logic and transmission gate circuits

UNIT II CMOS LOGIC CIRCUITS

CMOS Inverter - DC characteristics, Transient response, Layout and Parasitic capacitance, Noise immunity - Combinational Logic Design - CMOS NAND, NOR, XOR gates and complex logic gates, Propagation delay and Power dissipation - Series-parallel connections, Transmission gate based logic, Pass transistor logic, Multiplexer and Demultiplexer design

UNIT III SEQUENTIAL CIRCUITS AND MEMORY

CMOS Latch and Flip-Flop Design - SR Latch, D Latch, D Flip-Flop (master-slave), Design for timing and metastability. Memory Design - Registers, Static RAM (SRAM) cell design and array organization, Dynamic RAM (DRAM) - single transistor DRAM cell, Read, Write and Refresh operations

UNIT IV SUBSYSTEM DESIGN AND SYSTEM DESIGN

Multiplexer design, Decoder design, Arithmetic circuits, Adders - Ripple Carry Adder (RCA), Carry Look Ahead (CLA), Manchester Carry Chain, Multipliers - Array multiplier, Baugh-Wooley multiplier. Datapath design - Controller and datapath design using finite state machines, System design methodology

UNIT V VLSI DESIGN TOOLS AND METHODOLOGIES

Overview of VLSI Design Flow - Specification, Simulation, Synthesis, Place and Route, Verification and Testing. Design description using HDL - VHDL and Verilog overview, Simulation and Synthesis of digital circuits using HDL. VLSI Testing - Test Generation, Testability Design - Design for Testability (DFT). Introduction to VLSI Design tools - CAD tools, EDA tools, Physical design tools

TOTAL: 45 PERIODS

COURSE OUTCOMES:

At the end of the course the students will be able to

1. CO1: Analyse and design basic MOS circuits for given specifications
2. CO2: Design and evaluate CMOS logic circuits and gates
3. CO3: Design sequential circuits and memory structures
4. CO4: Design subsystems and systems using HDL
5. CO5: Verify and test VLSI designs and apply design methodology

TEXTBOOKS:

1. Neil H.E. Weste and David M. Harris, "CMOS VLSI Design: A Circuits and Systems Perspective", 4th Edition, Pearson Education, 2010. (Unit I-V)

REFERENCES:

1. Rabaey J.M, Chandrakasan A.P, Nikolic B, "Digital Integrated Circuits: A Design Perspective", 2nd Edition, Pearson Education, 2003.
2. Sung-Mo Hong & Mohab Anis, "Low Power Design in Deep Submicron Electronics", Kluwer Academic Publishers, 2004.
3. Kang Sung-Mo and Leblebici Yusuf, "CMOS Digital Integrated Circuits: Analysis and Design", 3rd Edition, Tata McGraw-Hill, 2003.