EE3302 Digital Logic Circuits Syllabus - Anna University
Explore the Anna University EE3302 Digital Logic Circuits syllabus for Electrical and Electronics Engineering students.
EE3302 DIGITAL LOGIC CIRCUITS
L T P C
3 0 0 3
COURSE OBJECTIVES:
- To introduce the fundamentals of combinational and sequential digital circuits.
- To study various number systems and to simplify the mathematical expressions using Boolean functions word problems
- To study implementation of combinational circuits using Gates` and MSI Devices.
- To study the design of various synchronous and asynchronous circuits
- To introduce digital simulation techniques for development of application oriented logic circuit
UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 9
Number system, error detection, corrections & codes conversions, Boolean algebra: De-Morgan's theorem, switching functions and minimization using K-maps & Quine McCluskey method - Digital Logic Families -comparison of RTL, DTL, TTL, ECL and MOS families - operation, characteristics of digital logic family.
UNIT II COMBINATIONAL CIRCUITS 9
Combinational logic - representation of logic functions-SOP and POS forms, K-map representations - minimization using K maps - simplification and implementation of combinational logic – multiplexers and de multiplexers - code converters, adders, subtractors, Encoders and Decoders.
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS 9
Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering - counters - asynchronous and synchronous type - Modulo counters - Shift registers - design of synchronous sequential circuits – Moore and Mealy models- Counters, state diagram; state reduction; state assignment.
UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC DEVICES
Asynchronous sequential logic Circuits-Transition stability, flow stability-race conditions, hazards &errors in digital circuits; analysis of asynchronous sequential logic circuits- introduction to Programmability Logic Devices: PROM – PLA –PAL, CPLD-FPGA.
UNIT V VHDL 9
RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers & De multiplexers).
TOTAL: 45 PERIODS